-- EXERCISE_1_1
entity EXERCISE_1_1 is
  port (
    IN_A, IN_B, IN_C, IN_D: in bit;
    OUT_A: out bit
  );
end EXERCISE_1_1;

architecture BEHAVIOR of EXERCISE_1_1 is
  signal INT_A, INT_B, INT_C, INT_D, INT_E: bit;
begin
  INT_A <= IN_A and INT_B;
  INT_B <= IN_B or IN_C;
  INT_C <= '1';
  INT_D <= INT_C or IN_B;
  INT_E <= IN_D and INT_D;
  OUT_A <= INT_A or INT_E;
end BEHAVIOR;


-- TESTBENCH
library ieee;
use ieee.std_logic_1164.all;
entity TESTBENCH is
end TESTBENCH;

architecture BEHAVIOR of TESTBENCH is
  signal TEST_IN_A, TEST_IN_B, TEST_IN_C, TEST_IN_D: bit;
  signal TEST_OUT_A: bit;
begin
  -- Instantiate the unit under test
  uut: entity work.EXERCISE_1_1(BEHAVIOR)
  port map(TEST_IN_A, TEST_IN_B, TEST_IN_C, TEST_IN_D, TEST_OUT_A);
  -- Generate test values
  process (TEST_IN_A, TEST_IN_B, TEST_IN_C, TEST_IN_D)
  begin
    TEST_IN_A <= not TEST_IN_A after  200 ns;
    TEST_IN_B <= not TEST_IN_B after  400 ns;
    TEST_IN_C <= not TEST_IN_C after  800 ns;
    TEST_IN_D <= not TEST_IN_D after 1600 ns;
    -- Break simulation
    assert false
      report "Break"
    severity failure;
  end process;
end BEHAVIOR;